(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a dynamic type RAM device which has a large memory capacity and low power consumption and which is used, for example, in an electronic computer.
(2) Description of the Prior Art
As illustrated in FIG. 1, a conventional MOS dynamic type RAM device comprises a row decoder RDEC, sense amplifier and column decoder group SAD which comprises column decoders CDEC1 through CDECm and sense amplifiers SA1 through SAm and which is located in the central portion of a memory chip, two memory cell groups MCG1 and MCG2 each comprising a plurality of memory cells and dummy cells and respectively located on the sides of the sense amplifier and column decoder group SAD, and an input/output amplifier AMP. The memory cell group MCGl comprises the memory cells MCjk (j=1, . . . , n/2; k=1, . . . , m) arranged in m columns and n/2 rows and m dummy cells DC1k (k=1, . . . , m) disposed in a row. The memory cell group MCG2 comprises the memory cells MCjk (j=n/2+1, . . . , n; k=1, . . . , m) arranged in m columns and n/2 rows and m dummy cells DC2k (k=1, . . . , m) disposed in a row. From the row decoder RDEC, n row lines or word lines WL1 through WLn extends in the longitudinal direction of FIG. 1 and each of the row lines WL1 through WLn is connected to m memory cells in a corresponding row of the memory cell groups MCG1 and MCG2. From the row decoder RDEC, two dummy row lines or dummy word lines DWL1 and DWL2 extend parallel to the row lines WL1 through WLn. The dummy row lines DWL1 and DWL2 are respectively connected to m dummy cells DC1k and DC2k in corresponding rows of memory cell groups MCG1 and MCG2 respectively. From the sense amplifiers SA1 through SAm, m pairs of bit lines BL1 and BL1 through BLm and BLm extend in a transverse direction in FIG. 1 and each of the bit lines is connected to the n/2 memory cells and the dummy cell of a corresponding column. On both sides of the sense amplifier and column decoder group SAD, a pair of bus lines BS and BS are arranged and connected to the input/output amplifier AMP. Each of the memory cells MCjk comprises a capacitor Cjk (j=1, . . . , n; k=1, . . . , m) and a MOS transistor QCjk having a gate electrode connected to one of the row lines WL1 through WLn and, and a source or drain electrode connected to one of the bit lines BL1 and BL1 through BLm and BLm. Each of the dummy cells DC1k and DC2k comprising a capacitor CD1k or CD2k (k=1, . . . , m), a MOS transistor QD1k or QD2k having a gate electrode is connected to the dummy row line DWL1 or DWL2 and a source or drain electrode connected to one of the bit lines BL1 and BL1 through BLm and BLm, and, a MOS transistor QR1k or QR2k connected in parallel with to the capacitor CD1k or CD2k of the dummy cell DC1k or DC2k respectively. Each sense amplifiers SA1 through SAm comprise a pair of cross coupled MOS transistors Qa11 and Qa12 through Qam1 and Qam2. The device also includes row commonly connected to the drain electrode of a MOS transistor QE and a drain electrode connected to a pair of the bit lines BL1 and BL1 through BLm and BLm and to a pair of the bus lines BS and BS through one of MOS transistors Q11 and Q12 through Qm1 and Qm2. The transistor pairs Q11 and Q12 through Qm1 and Qm2 are operated by the column decoders CDEC1 through CDECm respectively.
When reading of information from, for example, the memory cell MC11, the transistors QR11 through QR2m, has been previously turned on by a reset signal RST discharging electric charges of the capacitors CD11 through CD2m of the dummy cells DC11 through DC2m discharged, and the row line WL1 is selected by the row decoder RDEC and the potential of the row line WL1 becomes high potential. At the same time, the dummy row line DWL2 is selected and the potential of the dummy row line DWL2 becomes a high potential. Therefore, the transistor QC11 of the memory cell MC11 and the transistor QD21 of the dummy cell DC21 are both turned on, and, the capacitor C11 and the capacitor CD21 are respectively connected to the bit lines BL1 and BL1 through the transistors QC11 and QD21. Since the bit lines BL1 and BL1 are both, as is well known, precharged, for example, to a high potential and the capacitance of each of the memory cells MCjk is larger than that of each of the dummy cells CD1k and CD2k, the potential of the bit line BL1 becomes lower than that of the bit line BL1 if the capacitor C11 is not charged, i.e. if the information "0" is stored in the memory cell MC11.
Next, the clock signal LE becomes a high potential turning transistor QE on and enabling sense amplifiers SA1 through SAm. Since the potential of the gate electrode of the transistor Qa12, i.e., the potential of the bit line BL1, is lower than that of the gate electrode of the transistor Qa11, i.e., that of the bit line BL1 as mentioned above, the transistor Qa12 is turned off and the transistor Qa11 is turned on. Thus, the potential of the bit line BL1 becomes much lower and the potential of the bit line BL1 becomes much higher.
In this condition, the transistors Q11 and Q12 are both turned on by the column decoder CDEC1 and the bit lines BL1 and BL1 are respectively connected to the bus lines BS and BS. Therefore, the potentials of the bit lines BL1 and BL1 are respectively transferred to the bus lines BS and BS. The input/output amplifier AMP detectes the potential difference between the bus lines BS and BS and outputs a read out data Dout corresponding to the potential difference.
It should be noted that the smaller the stray capacitance of each of the bit lines BL1 and BL1, compared with the capacitance of each of the capacitors C11 and CD21, the larger the potential difference between the bit lines BL1 and BL1 becomes, enabling the sense amplifier SA1 to more easily and surely detect the potential difference of the bit lines. However, due to the increase in the integration density of memory devices the size of each of the memory cells is decreased and the number of memory cells connected to a bit line is increased, so that the stray capacitance of each of the bit lines increase and the capacitance of the capacitor of each of the memory cells decrease. Therefore, when the memory capacity of the memory device is very large, the potential difference between the bit lines connected to the same sense amplifier is decreased to a value near the lower limit of the differential input voltage of the sense amplifier so that it is very difficult to detect the potential difference of the bit lines.
Generally, in a 16 Kbit memory device having a memory cell array of 128.times.128 bits, the number of sense amplifiers is 128, and the number of memory cells connected to a bit line is 64. Thus, one row of 128 memory cells disposed in a column and one of the dummy cells are connected to one sense amplifier. In the 64 Kbit memory device having memory cell array of 256.times.256 bits, the number of the sense amplifiers is 256 and the number of the memory cells connected to a bit line is 128. Therefore, in the 64 Kbit memory device, the number of memory cells connected to a bit line is twice that of the 16 Kbit memory device and the length of each of the bit lines becomes longer, so that the stray capacitance of each bit line becomes large and the potential difference between the bit lines decreases accordingly. As a result, it is necessary to use sense amplifiers having high sensitivity.
In order to solve the above-mentioned problem, an arrangement of circuit components on a semiconductor chip of a memory device as illustrated in FIG. 2 can be used. In the arrangement of FIG. 2, two memory blocks BLK1' and BLK2' each of which comprises a sense amplifier and column decoder group SAD and two memory cell groups MCG arranged on both sides of the sense amplifier and column decoder group SAD. The row decoder RDEC selects one row from one of the memory blocks BLK1' and BLK2'. The column decoders in the sense amplifier and column decoder groups SAD of both memory blocks operate at the same time and select corresponding columns of the memory blocks BLK1' and BLK2'. In the arrangement of FIG. 2, when the memory capacity is 64 Kbit, each of the memory cell groups MCG has 64 rows and 256 columns, thus the number of the memory cells connected to a bit line is 64. Therefore, the potential difference between the bit lines can be the same as that of the 16 Kbit memory device, and it is not necessary to use highly sensitive sense amplifiers. In the memory device having a still larger memory capacity, for example, 256 Kbit or 512 Kbit, the number of the memory blocks is increased, so that the number of the memory cells connected to a bit line does not increase greatly. In this case, the sense amplifiers and the column decoders are both located in the central portion of each memory block.
However, in the above-mentioned arrangement, the area on the semiconductor chip of the memory device occupied by the sense amplifier and column decoder groups is relatively large, thus reducing the area available for memory cells. Therefore, the semiconductor chip area is not used effectively. For example, in the 64 Kbit memory device having the arrangement of FIG. 2, the width of each of the memory cell groups MCG on the semiconductor chip is approximately 500 to 600 .mu.m and the width of each of the sense amplifier and column decoder groups SAD is approximately 350 to 400 .mu.m. Therefore, the width of each one of the memory blocks BLK1' and BLK2' is approximately 1350 to 1600 .mu.m and each of the sense amplifier and column decoder groups SAD occupies approximately 25% of the area of each of the memory blocks BLK1' and BLK2'. Moreover, in semiconductor memory devices, other circuit components, such as the row decoder RDEC, are required and thus the area available for memory cells is further reduced.
Moreover, in the above-mentioned arrangement, the number of the column decoders driven by each of the column address buffers (not shown in the drawing) is large and, therefore, the load capacitance for each column address buffer is large, so that the operating speed of each of the column address buffers is decreased.